The present invention relates to methods of manufacturing and testing logic devices.
Many current methods of testing logic devices, such as embedded microprocessors, have been used commercially. One such method is known as scan testing. During scan testing at clock speeds approaching or at the processor speed, it has been historically difficult to diagnose propagation delay failures using certain types of testing patterns, such as stuck-at testing patterns. In addition, due to the large number of elements on many logic devices, it is very difficult to efficiently test all logic combinations. One technique to address this issue, is to selectively test some, but not all, logic combinations of the logic device. However, it would be more desirable to test all logic combinations to improve robustness and quality of the logic device. Another diagnostic testing method for logic devices uses hardware equipment such as microprobes or electronic beam equipment. However, such hardware methods can be expensive and time consuming. Further, in certain cases, these hardware testing methods may not be useful due to physical limitations of an integrated circuit including the logic device under test and limitations of the physical hardware equipment.
Accordingly, there is a need for an improve d method of making and testing logic devices.